Super-scalar computers and other computing devices include cells that each have one or more processing units (PUs) and memory for the cell. In connection with booting a cell, its memory must be checked for faulty locations so that such locations can be bypassed by the operating system executed by the cell. Typically, faulty location addresses are logged in a page de-allocation table (“PDT”), which is provided to the operating system so that the faulty locations can be avoided.
Generally speaking, memory tests fundamentally involve writing data (e.g., pseudo random pattern) to the memory, reading the data back, writing the complement of the data, and finally, reading the complement data. The read data is compared with the previously written data to determine whether they are the same indicating that the memory is healthy. This method effectively checks every bit in the memory system. It has been implemented in several ways, but essentially there are two conventional schemes: full comparison and machine check.
The full comparison method consists of one or more processors checking (writing/reading) the memory on a word by word basis. It is very thorough, but it is relatively slow. With this method, all processors can be used to check a separate block of the memory. However, with every-increasing memory size, even such a parallel implementation of the method can be excessively slow.
The machine check method uses a machine check handler, which carries out the actual memory error processing. Machine check handlers are normally included as part of conventional memory systems (e.g, within the operating system). A processor initiates the memory check handler, which generates an interrupt to the processor when a faulty location is encountered so that it may be logged by the processor. Typically, only a single processor is used with this mechanism because with multi-processor designs require excessively complex firmware (i.e., boot up routine). The single processor scheme functions adequately, but it fails to take advantage of the multiple processor resources available to a cell.
Accordingly, what is needed is an improved memory test method that can exploit the availability of multiple processors for implementing the test.